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Arbiters are electronic devices that allocate access to shared resources. == Bus arbiter == A bus arbiter is a device used in a multi-master bus system to decide which bus master will be allowed to control the bus for each bus cycle. The most common kind of bus arbiter is the memory arbiter in a system bus system. A memory arbiter is a device used in a shared memory system to decide, for each memory cycle, which CPU will be allowed to access that shared memory.〔 Michael Fingeroff. ("High-Level Synthesis Blue Book" ). 2010. p. 270. quote: "The bus or memory arbiter processes the request from the different processes and decides who gets access to the bus/memory." 〕〔 Arten Esa, Bryan Myers. ("Design of an Arbiter for DDR3 Memory" ). 2013. 〕〔 Kearney, D.A.; Veldman, G. ("A concurrent multi-bank memory arbiter for dynamic IP cores using idle skip round robin" ). 2003. DOI: 10.1109/FPT.2003.1275789. 〕 Some atomic instructions depend on the arbiter to prevent other CPUs from reading memory "halfway through" atomic read-modify-write instructions. A memory arbiter is typically integrated into the memory controller/DMA controller. Some systems, such as Conventional PCI, have a single centralized bus arbitration device that one can point to as "the" bus arbiter. Other systems use decentralized bus arbitration, where all the devices cooperate to decide who goes next. 〔 Tim Downey. ("Bus Arbitration" ) 〕〔 Shun Yan Cheung. ("Bus Arbitration" ) 〕 When every CPU connected to the memory arbiter has synchronized memory access cycles, the memory arbiter can be designed as a synchronous arbiter. Otherwise the memory arbiter must be designed as an asynchronous arbiter. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Arbiter (electronics)」の詳細全文を読む スポンサード リンク
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